In industrial applications, static parameters of an analog-to-digital converter (Analog-to-Digital Converter, ADC) need to be calculated. For the calculation of the static parameters of the ADC, it is required that an output code and a corresponding input voltage of the ADC need to be collected. However, because the transmission performance curve of the ADC is a many-to-one mapping function, the existing test circuit for testing the ADC is complex, and the required test time is rather long.
For example, in the prior art, a method such as a linear staircase histogram method or a bar chart method based on multi-point sampling is used to test the static parameters of the ADC, for example, an integral nonlinearity value (Integral nonlinearity, INL), a differential nonlinearity value (Differential Nonlinearity, DNL), and a gain error.
The linear staircase histogram method or the bar chart method is a statistical method, featuring randomness and roughness and incapable of determining the input voltage value of the ADC according to the output code output by the ADC. In the process of testing the ADC, a more accurate test result can be obtained only under conditions of sufficient sampling points, and consequently, the test time is rather long.
For example, for a 10-bit ADC, if the histogram method is used, the number of sampling points is (210)×16=1024×16=16384, and the sampling time is rather long.
Therefore, how to design a conversion circuit for shortening the ADC test time becomes a technical problem to be solved at present.